Previous: T3.1 --
T3.2 --
Next: T3.3
WP: WP3
Title: Active Sleeping
Start month: M4
M6 (Mar 2011)
End month: M21
M24 (Sep 2012)
Leader: ETY
Participants:
CNIT
MLX
LQDE
TEI
TELIT
VTT
ETY
LGT
INFO
Objectives:
- Identify mechanisms allowing the introduction of standby techniques into FPGAs, network processors and ASICs in network equipment.
- Identify the functionality required of sentinel hardware, which maintains network presence while a network interface is in standby mode.
- Design and develop mechanisms and architectures for standing by:
- redundant parts of core/metro network devices, while maintaining network presence.
- temporary unused/free terminations of access networks in a particular reference to VDSL DSLAM and home gateway.
- Design novel "traffic proxying" paradigms (at the FW or SW level) able to optimize the use of deep-sleeping primitives, and to be included into home gateways and/or DSLAMs. These paradigms will enable edge devices and network terminations to enter into sleeping modes, while maintaining their network presence.
- Introduce energy-aware building blocks to network interface boards, or evaluation boards, as appropriate.
- Design and optimize:
- home and access prototypes (home gateways and DSLAMs) with energy-aware building blocks and optimization policies.
- transport and core prototypes (routers and L2 switches, etc.) with energy-aware building blocks and optimization policies.
- multistage architectures for transport devices (routers and switches), exploiting load-balancing of traffic, and distributed routing backend, in which elements of the multistage network can be put in standby mode to save energy.
- Design and develop register/configuration interfaces of data-plane building-blocks for controlling hardware standby mechanisms, according to the specifications of T4.1 and T4.2.
