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T3.1 --
Next: T3.2
WP: WP3
Title: Power Scaling
Start month: M4
M6 (Mar 2011)
End month: M21
M24 (Sep 2012)
Leader: CNIT
Participants:
CNIT
MLX
LQDE
TELIT
DCU
VTT
ETY
LGT
Objectives:
- Identify mechanisms allowing the introduction of frequency scaling, voltage scaling and/or clock halting techniques into FPGAs, network processors and ASICs in network equipment., such as:
- FPGA power scaling through the dynamical allocation of bypass/active mode of system subunits, with respect to processing capability requirements.
- Exploring new 65 nm CMOS technology capabilities using full custom and analog design methods.
- Design and develop novel traffic handling, processing and shaping policies able to make optimal use of power scaling capabilities, and to respect QoS metrics (e.g., loss rates, maximum delays, jitter, etc.). In the early stage such policies will be evaluated through simulations and emulations, and then included as firmware/software in evaluation boards.
- Design and optimise with energy-aware building blocks and optimization policies:
- home and access prototypes (home gateways and DSLAMs).
- transport and core prototypes (routers and L2 switches).
- Incorporate support for power scaling, link interface of T3.3 and energy-aware building blocks in prototype platforms.
- Design and develop register/configuration interfaces of data-plane building-blocks for controlling hardware power scaling mechanisms, according to the specifications of T4.1 and T4.2.
